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zl2105 data sheet march 30 , 2011 fn6851.2 1 1 - 888 - intersil or 1 - 888 - 468 - 3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2009, 2013 . all rights reserved all other trademarks mentioned are the property of their respective owners not recommended for new designs rec ommended replacement part zl2102 3a integrated digital dc - dc converter figure 1 . block diagram description the zl2105 is an innovative power conversion and management ic that combines an integrated synchronous step - down dc - dc converter wit h key power management functions in a small package, resulting in a fl exible and integrated solution. zilker labs digital - dc? technology enables unparalleled power management integration while delivering industry - leading performance in a tiny footprint. the zl2105 can provide an output voltage from 0.6 v to 5.5 v from an input voltage between 4.5 v and 14 v. internal 4.5 a low r ds ( on ) synchronous power mosfets enable the zl2105 to deliver continuous loads up to 3 a with high efficiency, and an internal schottky bootstrap diode further re duces discrete component count. the zl2105 also supports phase spreading for reduc ed system capacitance. power management features such as digital soft - start delay and ramp, sequencing, tracking, and margining can be configured by simple pin - strapping or through an on - chip serial port. the zl2105 uses standard pmbus? protocol for communicating with other devices to provide intelligent system power management. features power conversion ? high efficiency ? 3 a continuous output current ? i ntegrated mosfet switches ? 4.5 v to 14 v input range ? 0.54 v to 5.5 v output range (with margin) ? 1% output voltage accuracy ? 200 khz to 2 mhz switching frequency ? supports phase spreading ? small footprint (6 x 6 mm qfn package ) power management ? digital soft s tart/stop ? precision delay and ramp - up ? power good/e nable ? voltage tracking, sequencing, and margining ? output voltage/current monitoring ? thermal monitor w/ shutdown ? non - volatile memory ? i 2 c/smbus? communication bus ? pmbus compatible applications ? telecom and sto rage equipment ? digital set - top box ? industrial supplies ? 12 v d istributed power systems ? point of load converters 2 . 5 v l d o p w m c o n t r o l & d r i v e r s v i n v o u t s d a s c l s a l r t v d d p v r 2 v 5 v d d s b s t v s e n v d d p p o w e r m g m t m g n t r k u v l o s s v 0 v 1 p g e n c f g s y n c c h g p u m p c p 1 c p 2 s w s w p g n d 5 v l d o v r a s m b u s d l y s a v d r v d d l p g n d n v m x t e m p t e m p s e n s e
zl2105 2 fn6851.2 march 30 , 2011 table of contents 1. electrical characteristics ................................ ................................ ................................ ................................ ............... 3 2. pin descriptions ................................ ................................ ................................ ................................ ............................ 6 3. typical application circuit ................................ ................................ ................................ ................................ ........... 8 4. zl2105 overview ................................ ................................ ................................ ................................ ....................... 10 4.1 digital - dc architecture ................................ ................................ ................................ ................................ ........ 10 4.2 power conversion overview ................................ ................................ ................................ ................................ 11 4.3 power management overview ................................ ................................ ................................ .............................. 12 4.4 multi - mode pins ................................ ................................ ................................ ................................ .................... 12 5. power conversion functional description ................................ ................................ ................................ .................. 13 5.1 internal bias regulators and input supply connections ................................ ................................ ...................... 13 5.2 high - side driver boost circuit ................................ ................................ ................................ ............................. 13 5.3 low - side driver supply option s ................................ ................................ ................................ .......................... 13 5.4 dual input supply configuration ................................ ................................ ................................ .......................... 14 5.5 output voltage selection ................................ ................................ ................................ ................................ ....... 15 5.6 start - up procedure ................................ ................................ ................................ ................................ ................. 15 5.7 soft start delay and ramp times ................................ ................................ ................................ ......................... 16 5.8 switching frequency and pll ................................ ................................ ................................ .............................. 17 5.9 component selection ................................ ................................ ................................ ................................ ............ 19 5.10 current sensing and current limit threshold selection ................................ ................................ .................... 22 5.11 loop compensation ................................ ................................ ................................ ................................ ............ 22 5.12 non - linear response (nlr) settings ................................ ................................ ................................ .................. 23 5.13 efficiency optimized drive dead - time control ................................ ................................ ................................ . 24 6. power management functional description ................................ ................................ ................................ ............... 24 6.1 input undervoltage lockout ................................ ................................ ................................ ................................ . 24 6.2 power good (pg) and output overvoltage protection ................................ ................................ ......................... 25 6.3 output overvoltage protection ................................ ................................ ................................ ............................. 25 6.4 output pre - bias protection ................................ ................................ ................................ ................................ ... 25 6.5 output overcurrent protection ................................ ................................ ................................ .............................. 26 6.6 thermal overload protection ................................ ................................ ................................ ................................ 26 6.7 voltage tracking ................................ ................................ ................................ ................................ ................... 27 6.8 voltage margining ................................ ................................ ................................ ................................ ................ 28 6.9 i 2 c/smbus communications ................................ ................................ ................................ ................................ 29 6.10 i 2 c/smbus device address selection ................................ ................................ ................................ ................ 29 6.11 phase spreading ................................ ................................ ................................ ................................ .................. 29 6.12 output seque ncing ................................ ................................ ................................ ................................ .............. 30 6.13 monitoring via i 2 c/smbus ................................ ................................ ................................ ................................ . 31 6.14 temperature monitoring using the xtemp pin ................................ ................................ ................................ . 31 6.15 non - volatile memory and device security features ................................ ................................ ......................... 32 7. package dimensions ................................ ................................ ................................ ................................ .................... 33 8. ordering infor mation ................................ ................................ ................................ ................................ .................. 34 9. related documentation ................................ ................................ ................................ ................................ ............... 34 10. revision history ................................ ................................ ................................ ................................ ........................ 35
zl2105 3 fn6851.2 march 30 , 2011 1. electrical characteristics tab le 1 . absolute maximum ratings voltage measured with respect to sgnd. operating beyond these limits may cause permanent damage to the device. functional operation beyond the recommended operating conditions is not implied. parameter pin comments value unit dc supply voltage vddp, vdds , vdr - 0.3 to 17 v logic supply voltage v ddl optional - 0.3 to 6 .5 v high side supply voltage bst - 0.3 to 25 v high side boost voltage bst - sw - 0.3 to 8 v switch node current sw sink or source 4. 5 a internal drive references vr, vra - 0.3 to 6 .5 v internal 2.5 v reference v25 - 0.3 to 3 v logic i/o voltage en, mgn, pg , sda, scl, sa, salrt, ss, dly, sync, v trk, uvlo, v(0,1), ilim, vsen, cfg - 0.3 to 6 .5 v ground differential dgnd - sgnd pgnd - sgnd 0.3 v mosfet drive reference current vr 30 ma analog reference current vra 150 ma 2.5 v reference current v25 60 ma junction temperature C - 55 to 150 c storage temperature C - 55 to 150 c lead temperature all soldering, 10 s 300 c ta ble 2 . recommended operating conditions and thermal information parameter symbol min typ max unit input supply voltage range, vddp, vdds (see figure 8 ) vdds tied to vr , vra 4.5 C 5.5 v vr , vra floating 5 C 14 v logic supply voltage range , v ddl v ddl (optional) 3.0 C 5.5 v internal driver supply, vdr vdr 10 C 14 v output voltage range 1 v out 0.54 C 5 .5 v operating junction temperature range t j - 40 C 12 5 c junction to ambient thermal imp edance 2 ja C 35 C c/w junction to case thermal impedance 3 jc C 5 C c/w notes: 1. includes margin 2. ja is measured in free air with the device mounted on a multi - layer fr4 test board and the exposed metal pad soldered to a low impedance ground plane using multipl e vias. 3. for jc , the case temperature is measured at the center of the exposed metal pad . see figure 4 for thermal derating.
zl2105 4 fn6851.2 march 30 , 2011 table 3 . electrical specifications v dd p = v dds = 1 2 v, t a = - 4 0 c to 85 c unless otherwise noted. typical values are at t a = 25 c . parameter conditions min (note 3 ) typ max (note 3) unit input and supply characteristics i dd s s upply c urrent f sw = 200 khz, no load f sw = 1 mhz, no load C C 2 5 3 6 ma ma i dd l supply current f sw = 200 khz, no load f sw = 1 mhz, no load C C 8 10 16 20 ma ma i dds shutdown current en = 0 v, vddl tied to vra , no i 2 c/smbus activity C 0.7 2 ma i ddl shutdown current en = 0 v, vddl = 5 v , no i 2 c/smbus activity C 2 25 50 0 a vr reference output voltage v dd > 5.5 v, i vr < 5 ma 4.5 5.2 5.5 v vra reference output voltage v dd > 5.5 v, i vra < 35 ma 4.5 5.2 5.5 v v25 reference output voltage i v25 < 50 ma 2.25 2.5 2.75 v output characteristics output current C C 3 a output voltage adjustment range 1 v in > v out 0.6 C 5.0 v output voltage setpoint resolution set using resistors C 10 C mv set using i 2 c/smbus C 0.025 C % fs vsen output voltage accuracy includes line, load, temp - 1 C 1 % vsen input bias current vsen = 5.5 v C 100 200 a soft start delay duration range 2 set using dly pin or resistor 7 C 200 ms set using i 2 c/smbus 0.007 C 500 s soft start delay duration accuracy C 6 C ms soft start ramp duration range set using ss pin 10 C 100 ms set using resist or or via i 2 c 0 C 200 ms soft start ramp duration accuracy C 100 C s logic input/output characteristics logic input current en, scl, sda pins - 250 250 na logic input low, v il C C 0.8 v logic input open (n/c) multi - mode logic pins C 1.4 C v log ic input high, v ih 2.0 C C v logic output low, v ol i ol 4 ma C C 0.4 v logic output high, v oh i oh - 2 ma 2.25 C C v tracking vtrk input bias current vtrk = 5.5 v C 110 200 a vtrk tracking accuracy 100% tracking, v out - vtrk - 100 C + 100 mv no tes: 1. does not include margin 2. the device requires approximately 6 ms following an enable signal and prior to output ramp. the minimum settable delay is 7 ms. 3. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. table 3 is continued on the following page
zl2105 5 fn6851.2 march 30 , 2011 table 3 . electrical characteristics (c ontinued) v ddp = v dds = 12 v, t a = - 40 c to 85 c unless otherwise noted. typical values are at t a = 25 c. parameter conditions min (note 3 ) typ max (note 3 ) unit oscillator and switching characteristics switch node current, i sw sourcing or sinking C 3 4. 0 a switching frequency range 200 C 2000 khz switching frequency set - point accuracy predefi ned settings - 5 C 5 % minimum sync pulse width 150 C C ns input clock frequency drift tolerance external clock source - 13 C 13 % maximum duty cycle 90 C C % r ds(on) of high side n - channel fets i sw = 1 a , v gs = 4.7 v C 125 1 80 m ? r ds(on) of low side n - channel fets i sw = 1a , v gs =8.5v, charge pump C 123 14 0 m ? i sw = 1a , v gs =12v C 11 4 1 30 m ? fault protection characteristics uvlo threshold range 3.79 C 13.2 v uvlo setpoint accuracy - 2 C 2 % uvlo hysteresis factory default C 3 C % configurable via i 2 c/smbus 0 C 100 % uvlo delay C C 2.5 s power good low threshold factory default C 90 C % v out power good high threshold factory default C 115 C % v out power good hysteresis factory default C 5 C % power good delay using pin - strap or resistor 1 0 C 200 ms configurable via i 2 c/smbus 0 C 500 s vsen undervoltage threshold factory default C 85 C % v out configurable via i 2 c/smbus 0 C 110 % v out vsen overvoltage threshold factory default C 115 C % v out configurable via i 2 c/ smbus 0 C 115 % v out vsen undervoltage hysteresis C 5 C % v o vsen undervoltage/ overvoltage fault response time factory default C 16 C s configurable via i 2 c/smbus 5 C 60 s peak current limit threshold 0.2 C 4.5 a current limit setpoint accuracy using ilim pin or via i 2 c/smbus C 100 C ma current limit shutdown delay factory default C 5 C t sw 2 configurable via i 2 c/smbus 1 C 32 t sw 2 thermal protection threshold (junction temperature) factory default C 125 C c configurable via i 2 c/smbus - 40 C 125 c thermal protection hysteresis C 15 C c notes: 1. factory default power good delay is set to the same value as the soft start ramp time. 2. t sw = 1/f sw , where f sw is the switching frequency. 3. compliance to datasheet limits is assured by one or more m ethods: production test, characterization and/or design.
zl2105 6 fn6851.2 march 30 , 2011 2. pin descriptions figure 2 . zl2105 pin configurations (top view) table 4 . pin descriptions pin label type 1 description 1 dgnd pwr digital ground. common return for digital signals. connect to low impedance ground plane. 2 sync i/o , m clock synchronization input . used to set switching frequency of internal clock or for synchronization to ext ernal frequency reference. programmable open drain output. factory default is push - pull 3 sa i,m serial address pin used to assign unique smbus address to each ic. 4 uvlo i,m sets the input undervoltage lockout threshold that disables the device. 5 ilim i, m sets the current limit threshold level. 6 scl i/o s e rial clock si gnal for system communications. 7 sda i/o s erial data signal for syste m communications. 8 salrt o smbus alert signal. 9 xtemp i external temperature sensor input. 10,11 v0, v1 i, m output voltage select pins. used to set the output voltage. 12 dly i, m soft start delay select pin . sets the delay from when en is asserted until the output voltage starts to ramp. 13 ss i, m digital soft - start/stop. sets the ramp period for the output to reach the desired regulation point (after soft - start delay period, if applicable). 14 vtrk i tr ack input. allows the output to track another voltage . 15 vsen i output voltage positive feedback sensing node. 16 nc - no internal connection. 1 7 v dr pwr supply pin for internal drivers. 1 8 , 19 cp1,cp2 i/o level - shift charge pump for 5 v operation. connect external capacitor. notes: 1. i = input, o = output, pwr = power or ground . m = multi - m ode pins. u v l o i l i m s c l s d a s a l r t x t e m p d g n d s a s y n c z l 2 1 0 5 v d d p s w s w p g n d p g n d c p 2 v r v d d p b s t m g n f c v 2 5 v d d s v d d l v r a p g c f g e n s s v t r k v s e n n c v d r c p 1 v 0 d l y v 1 e x p o s e d p a d d l e c o n n e c t t o s g n d 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8
zl2105 7 fn6851.2 march 30 , 2011 table 4 . pin descriptions (continued ) pin label type 1 description 20,21 pgnd pwr power ground. common return for internal switching mosfets. 22,23 sw i/o switching node (level - shift common). 24,25 vddp pwr bias power for internal switching mosfets (return is pgnd). 26 bst pwr bootstrap v dd for level - shift driver (referenced to sw). 27 vr pwr regulated bias from internal 5v low - dropout regulator (ret urn is pgnd). decouple with a 4.7 f capacitor to pgnd . connect 91? resistor between vr and vra. 28 vr a pwr regulated 5 v bias for internal analog circuitry (return is sgnd). decouple with a 4.7 f capacitor to sgnd. connect 91? resistor between vr and vra. 29 vddl pwr i nternal logic supply. connect to vra or apply a 3.0 - 5.5 v external supply. return is sgnd . 30 vdds pwr ic supply voltage (return is sgnd). 31 v25 pwr regulated bias from internal 2.5 v low - dropout regulator. decouple with a 10f capacitor. 32 fc i freq uency compensation select pin. used to s et loop compensation. 33 mgn i signal that enables margining of output voltage. 34 cfg i configuration pin. sets switching phase delay and sequencing order. 35 en i enable input. active high signal enables the device. 36 pg o power good output. this pi n transitions high 100 ms after output voltage stabilizes within regul ation band. programmable open drain output. factory default is open drain. epad sgnd pwr exposed thermal pad. common return for analog signals ; internal connection to sgnd. connect to l ow impedance ground plane. notes: 1. i = input, o = output, pwr = power or ground. m = mul ti - mode pins. please refer to section 4.4 multi - m ode pins , on page 12 .
zl2105 8 fn6851.2 march 30 , 2011 3. typical application circuit the following application circuit represent s a typical implementation of the zl2105. figure 3 . 12 v to 3.3 v / 3 a application circuit (10.8 v uvlo, 10 ms ss delay, 5 0 ms ss ramp, 12 v used for low - side fet driver ) u v l o i l i m s c l s d a s a l r t x t e m p d g n d s a s y n c z l 2 1 0 5 v d d p s w s w p g n d p g n d c p 2 v r v d d p b s t m g n f c v 2 5 v d d s v d d l v r a p g c f g e n s s v t r k v s e n n c v d r c p 1 v 0 d l y v 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 v o u t 3 . 3 v v i n 1 2 v i 2 c / s m b u s e n a b l e p g o o d c b 4 7 n f c r 4 . 7 f c r a 4 . 7 f c 2 5 1 0 f c d d 2 . 2 f c d r 1 0 0 n f c o u t 1 5 0 f e p a d ( s g n d ) l o u t 4 . 7 h c i n 1 0 0 f r v r 9 1 ? f . b . * * f e r r i t e b e a d i s o p t i o n a l f o r i n p u t n o i s e s u p p r e s s i o n
zl2105 9 fn6851.2 march 30 , 2011 for all applications, the zl2105 must be derated according to the safe operating area (soa) curve s . figure 4 . zl2105 soa curves max conversion ratio vs switching frequency t j < 125 c 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 f sw (mhz) v out / v in v out may not exceed 5.5v at any time s w i t c h i n g f r e q u e n c y , f s w ( m h z ) o u t p u t v o l t a g e , v o u t ( v ) 1 2 3 1 . 4 1 . 2 1 . 0 0 . 8 0 . 6 0 . 4 0 . 2 z l 2 1 0 5 s o a v s f r e q u e n c y 4 5 v i n = 1 2 v v i n = 5 v v i n = 4 . 5 v t j 1 2 5 c l = 2 . 2 h 1 . 6 1 . 8 2 . 0 c i r c u i t f r o m f i g u r e 3 e x c e p t l = 2 . 2 h . a p p r o p r i a t e l s h o u l d b e s e l e c t e d a s d e s c r i b e d i n s e c t i o n 5 . 9 o f d a t a s h e e t
zl2105 10 fn6851.2 march 30 , 2011 4. zl2105 o verview 4.1 digital - dc architecture the zl2105 is a n innovative mixed - signal power conversion and power management ic based on zilker labs patented digital - dc technology that provides a n integrated, high performance step - down converter for point of load applications. the zl2105 integrates all necessary pwm control circuitry as well as s ynchronous 4.5 a n - channel mosfets in order to provide an extremely small solution for providing load currents up to 3 a. its unique pwm loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion proces s with no software required, resulting in a very flexible device that is also very easy to use. an extensive set of power management functions are fully integrated and can be configured using simple pin connections . the user configuration can be saved in a n internal non - volatile memory (nvm). additionally , all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility . once enabled, t he zl2105 is immediately ready to regulate power and perform power management tasks with no programmi ng required. advanced configu ration options and real - time configuration changes are available via the i 2 c/ smbus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller . integrated sub - regulation circuitry enables single supply operation from a ny supply between 4.5 v and 14 v with no secondary bias supplies needed . the zl2105 can also be configured to operate from a 3.3 v or 5 v standby supply when the main power rail is not present, allowing the user to configure and/ or read diagnostic information from the device when the main power has been interrupted or is disabled. the zl2105 can be configured by simply connecting i ts pins according to the tables provided in the foll owing sections. additionally, a comprehensive set of tools and application notes are available to help simplify the design process. an evaluation board is also available to help the user b ecome familiar w ith the device. this board can be evaluated as a standalone platform using pin configuration settings . a windows ? - based gui is also provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable . application notes and reference designs are available to assist the user in designing t o specific application demands. please register for my zl on www.intersil.com/zilkerlabs/ to access the most up - to - date documentation or call your local zilker labs sales office to order an evaluation kit.
zl2105 11 fn6851.2 march 30 , 2011 4.2 power conversion overview the zl2105 operates as a voltage - mode, synchronous buck converter with a selectable constan t frequency pwm contr ol scheme. the zl2105 incorporates dual low r ds(on) synchronous mosfets to help minimize the required circuit footprint. figure 6 . synchronous buck converter figure 6 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step - down converter, as the output voltage must always b e lower than the input voltage. the zl2105 integrates two mo sfets; qh is the top control mosfet and ql is the bottom sy nchronous mosfet. the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by the following equation: du ring time d, qh is on and v in C v out is applied across the inductor. as shown in figure 5 , the output voltage is di rectly applied to the vsen pin. the vsen signal is then compared to an internal programmable refere nce voltage that is set to the desired output voltage lev el. the error signal derived from this comparison is converted to a digital value with a fast ana log to digital (a/d) converter. the digital signal is also applied to an adjustable digital compensati on filter, and the compensated signal is used to derive the appropriate pwm duty cycle fo r driving the internal mosfets. the zl2105 also incorporates a non - linear response (nlr) loop to improve the response time and reduce the output deviation as a result of a load transient. the zl2 1 05 monitors the power converters operating conditions and continuously adjusts the turn - on and turn - off timing of the high - side and low - side mosfets to optimize the overall efficiency of the power supply. figure 5 . zl2105 block diagram in out v v d v i n v o u t q h q l l 1 c o u t z l 2 1 0 5 c i n c b d b p w m l d o nlr digital compensator input voltage bus v out bst digital compensator d - pwm + - vsen reset sync pll power management temp sensor mux xtemp mgn en v(0,1) pg sa ss vr sw ilim vdd communication ref sync gen vtrk vdds scl sda salrt > > adc adc adc fc ldo vddp i sense mosfet drivers chg pump cp1 cp2 dly cfg vra vddl vdr i sense vr nvm nlr digital compensator input voltage bus v out bst digital compensator d - pwm + - vsen reset sync pll power management temp sensor mux xtemp mgn en v(0,1) pg sa ss vr sw ilim vdd communication ref sync gen vtrk vdds scl sda salrt > > adc adc adc fc ldo vddp i sense mosfet drivers chg pump cp1 cp2 dly cfg vra vddl vdr i sense vr nvm
zl2105 12 fn6851.2 march 30 , 2011 4.3 power management ove rview the zl2105 incorporates a wide range of configurable power management features that are simple to impleme nt with no external components. additionally, the zl2105 includes circuit protection features that continuously safeguard the device and load fro m damage d ue to unexpected system faults. t he zl2105 can continuously monitor input voltage, output voltage/current, internal temperature, and the temperature o f an external thermal diode . a power good output signal is also included to enable power - on rese t functionality for an external processor. all power management functions can be c onfigured using either pin configuration techniques (see figure 7 ) or via the i 2 c/ smbus interface. monitoring parameters can also be pr e - configured to provide alerts for specific conditions . see application note an 20 13 for more details on smbus monitoring. 4.4 multi - m ode pins most power management features can b e configured using the multi - mode pins. the multi - mode pins can respond to fou r different connections as shown in table 5 . these pins are sampled when power is applied or by issuing a pmbus restore comman d (see application note an 20 13). pin - s trap settings : using this method, each pin can tak e on one of three possible states: low , open, or high. these pins can be connected to the vr or v25 pins for logic high settings, as either pin provides a regulated voltage higher than 2 v . using a single pin one of three settings can be selected, and usin g two pins the user can select one of nine settings. table 5 . multi - mode pin configuration pin tied to value low (logic low) < 0.8 vdc open (n/c) no connection high (logic high) > 2.0 vdc resistor to s gnd set by resistor value figure 7 . pin - strap and resistor setting examples resistor settings : this method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi - mode pin and sgnd. stan dard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associa ted with the resistor accuracy. a total of 25 unique sel ections are available using a single resistor . i 2 c/smbus method: almost any zl2105 function can be configured via the i 2 c/smbus interface using standard pmbus commands. additionally, any value that ha s been configured using the pin - strap or resistor settin g methods can also be re - configured and/or verified via the i 2 c/smbus. see application note an 20 13 for more details. the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa pin. vout_max is determined as 10% greater than the voltage set by the v0 and v1 pins. z l 2 1 0 5 m u l t i - m o d e p i n z l 2 1 0 5 r s e t l o g i c h i g h l o g i c l o w o p e n p i n - s t r a p s e t t i n g s r e s i s t o r s e t t i n g s m u l t i - m o d e p i n
zl2105 13 fn6851.2 march 30 , 2011 5. power conversion functional d escription 5.1 internal bias regulators and input supply connections the zl2105 employs three internal low dropout (ldo) regulators to supply bias voltages for internal circuitry as follows: vr: the vr ldo provides a regulated 5 v bias supply f or the mosfet driver circuits. it is powered from the vdds pin . a 4.7 f filter capacitor is require d at the vr pin. vra: the vra ldo provides a regulated 5 v bias supply for the current sense circu it and other analog circuitry. it is powered from the vdds pin . a small filter capacitor is required at the vra pin. for single supply operation, this pin sho uld be connected to the vddl pin so the vra ldo can be used to power the digital core logic circuitry. v25: the v25 ldo provides a regulated 2.5 v bias supply for the main controller circuitry. it is powered from the vddl pin . a 10 f filter capacitor is r equired at the v25 pin. when the input supply (vdds) is higher than 5.5 v, the vr and vra pin s should not be connected to any other pin s . they should have a filter capacitor and a 91? resistor attached as shown in figure 8 . due to the dropout voltage associated with the vr and vra bias regulator s , the vdds pin must be connected to the vr and vra pin s for designs operating from a supply below 5.5 v. figure 8 illustrates the r equired connections for both cases. figure 8 . input supply connections note: the internal bias regulators , vr and vra, are not designed to be output s for powering other circuitry. do not attach external loads to either of these p ins. the multi - mode pins may be connected to the v25 pin for logic high settings. 5.2 high - side driver boost circuit the gate drive voltage for the high - side mosfet driver is generated by a floating bootstrap capacitor , c b (see figure 6 ). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through diode d b . when ql turns off and the upper mosfet (qh) turns on, the sw node is pulled up to v ddp and the voltage on the bootstrap capacitor is boosted approximately 5v above v ddp to provide the necessary voltage to power the high - side driver. an internal schottky diode is used with c b to help maximize the high - side dri ve supply voltage. 5.3 low - side driver supply options the zl2105 provides multiple options for powering the internal low - side mosfet drivers as follows: 12 v supply: when operating from a 12 v input supply (or any supply 9 v or higher) , efficiency can be optimized by operating the l ow - side mosfet driver d irectly from the input supply. connecting the input supply to the v dr pin (with no external capacitor connect ed between cp1 and cp2) applies the input supply directly to the low - side driver. this is the simplest method of powering th e low - side driver and requires the fewest components. figure 9 illustrates the required connections for implementing this configuration. figure 9 . using an external 12 v supply to power the low - side driver v i n v d d s v r z l 2 1 0 5 5 . 5 v < v i n 1 4 v 4 . 5 v v i n 5 . 5 v v r a v i n v d d s v r z l 2 1 0 5 v r a 9 1 ? v r b s t v d d p v d d p s w s w p g n d p g n d c p 2 c p 1 v d r v r a v d d l v d d s 1 2 v 1 2 v z l 2 1 0 5 v o u t s g n d
zl2105 14 fn6851.2 march 30 , 2011 internal charge pump: a voltage doubler circuit can be used to optimize eff iciency when operating from a n input supply that is below 9 v or may occasionally drop below 9 v . the internal charge pump is enabled by connecting a 10 nf capac itor between the cp1 and cp2 pins and a 100 nf capacitor between vdr and pgnd . t he charge pump provides a low - side driver supply based on the equation below : v cp = (vr - 0.5v) x 2 figure 10 . using the internal charge pump to powe r the low - side driver the required connections are shown in figure 10 . note: when the input supply is always lower than 5.5 v, the vdds pin must be connected to the vr pin as shown in figure 11 . the resistor between vr and vra is not required when vddl and vdds are tied directly to vr and vra since this configuration overrides the internal ldos. figure 11 . powering the low - side driver when vdds 5.5 v 5.4 dual input supply configuration the zl2105 allows the use of two unique input supplies to enable communication with the device when the prim ary power rail is not present. typical applications of this scenari o use a 12 v supply as the main power input and either a 3.3 v or 5 v standby supply to power the device during periods when the primary power supply is disabled or not operationa l. this configuration allows a host controller to communicate with the zl2105 when the 12 v main supply is not available. figure 12 shows the typical connections required for this configuration. this figure uses the 12 v supply for powering the low - side driver. figure 12 . dual input supply operation v r b s t v d d p v d d p s w s w p g n d p g n d c p 2 c p 1 v d r v r a v d d l v d d s z l 2 1 0 5 5 v v o u t s g n d 1 0 n f 1 0 0 n f v r b s t v d d p v d d p s w s w p g n d p g n d c p 2 c p 1 v d r v r a v d d l v d d s z l 2 1 0 5 5 v t o 1 2 v v o u t s g n d 1 0 n f 1 0 0 n f v r b s t v d d p v d d p s w s w p g n d p g n d c p 2 c p 1 v d r v r a v d d l v d d s 1 2 v 1 2 v z l 2 1 0 5 v o u t 3 . 3 v / 5 v s g n d
zl2105 15 fn6851.2 march 30 , 2011 5.5 output voltage selection the output voltage may be set to any voltage between 0. 6 v and 5 . 0 v provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification . using the pin - strap method, v out can be set to any of nine standard voltages as shown in table 6 . table 6 . pin - strap output voltage settings v0 low open high v1 low 0.6 v 0.8 v 1 .0 v open 1.2 v 1.5 v 1.8 v high 2.5 v 3.3 v 5 .0 v t he resisto r setting method can be used to set the output voltage to levels not available in table 6 . r esistors r0 and r1 are selected to produce a specific voltage between 0.6 v and 5. 0 v in 10 mv steps. resistor r1 provides a co a rse setting and resistor r0 provides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (th is typically adds 1.4% error). to set v out using resistors, follow the steps below to calculate an index value and then use table 7 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1 : index1 = 4 x v out (v out in 10 mv steps) 2. round the result down to the nearest whole number . 3. select the value o f r1 f rom table 7 using the index1 rounded value from step 2 . 4. calculate index0: index0 = 100 x v out C (25 x index 1) 5. select the value of r0 from table 7 using the index0 value from step 4. table 7 . resistor s for setting output voltage index r 0 or r1 index r 0 or r1 0 10 k 13 34.8 k 1 11 k 14 38.3 k 2 12.1 k 15 42.2 k 3 13.3 k 16 46.4 k 4 14.7 k 17 51.1 k 5 16.2 k 18 56.2 k 6 17.8 k 19 61.9 k 7 19.6 k 20 68.1 k 8 21.5 k 21 75 k 9 23.7 k 22 82.5 k 10 26.1 k 23 90.9 k 11 28.7 k 24 100 k 12 31.6 k example: for v out = 1.33 v , index1 = 4 x 1.33 v = 5.32 ; from table 7 , r1 = 16 . 2 k ? index0 = (100 x 1.33 v) C (25 x 5 ) = 8 ; from table 7 , r0 = 21.5 k ? figure 13 . output voltage resistor setting example the output voltage may also be set to any value between 0.6 v and 5.5 v using the i 2 c interface. see application note an 20 13 for details. z l 2 1 0 5 v 1 v 0 r 0 2 1 . 5 k r 1 1 6 . 2 k v i n v o u t 1 . 3 3 v v d d p s w v d d s
zl2105 16 fn6851.2 march 30 , 2011 5.6 start - up procedure the zl2105 follows a specific internal start - up procedure after power is applied to the vdd pins ( vddl, vddp, and vdd s). table 8 d escribes the start - up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the en pin. the device requires approximately 10 - 20 ms to check for specific values stored in its internal memory. if the user has stored values in memor y, those values will be loaded. the device will then check the status of all multi - mode pins and load the values associated with the p in settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requi res approximately 7 ms before its output voltage may be allowed to start it s ramp - up process. if a sof t - start delay period less than 7 ms has been con figured (using pmbus commands ) , the device will default to a 7 ms delay period. if a delay period gr eater than 7 ms is configured, the device will wait for the configured delay peri od prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre - configured soft - start ramp time that has been set using th e ss pin . 5.7 soft start delay and ramp t imes in some applications, it may be necessary to set a delay from when an enable signal is received until the output voltage start s to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic i s turned on. the zl2105 gives the system designer several options for precisely and independently controlling both th e delay and ramp time periods. the soft - start delay period begins when the en pin is asserted and en ds when the delay time expires. the soft - start delay period is set using the dly pin. the soft - start ramp timer enable s a precisely controlled ramp to the nominal v out value that begins onc e the delay period has expired. the ramp - up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft - start delay and ramp times can be set to one of three s tand ard values according to table 9 and table 10 respectively. table 9 . soft start delay settings dly pin setting soft start delay time low 10 ms open 5 0 ms high 10 0 ms table 8 . zl2105 start - up sequence step # step name description time duration 1 power applied input voltage is applied to the zl2105s vdd pins (vddl, vddp, vdds) depends on input supply ramp time 2 internal memory check the device will check for values stored in its internal memory. this step is also performed after a restore command. approx 10 - 20 ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi - mode pin check the device loads values confi gured by the multi - mode pins. 4 device ready the device is ready to accept an enable signal. 5 pre - ramp delay the device requires approximately 6 ms following an enable signal and prior to ramping its output. additional pre - ramp delay may be configure d using the dly pin. approximately 6 ms
zl2105 17 fn6851.2 march 30 , 2011 table 10 . soft start ramp settings ss pin setting soft start ramp time low 10 ms open 5 0 ms high 10 0 ms if the desired soft start delay and ramp times are not one of the values listed in table 9 and table 10 , the times can be set to a custom value by connecting a resistor from the dly or ss pin to s gnd using the appropriate resistor values from table 11 . the value of this resistor is measured upon start - up or restore and will not change if the resistor is varied after power has been applied to the zl2105. see figure 14 for typical connect ions using resistors. figure 14 . dly and ss pin resistor connections table 11 . dly and ss resistor values dly or ss r dly or r ss dly or ss r dly or r ss 0 ms 10 k 110 ms 28.7 k 10 ms 11 k 120 ms 31.6 k 20 ms 12.1 k 130 ms 34.8 k 30 ms 13.3 k 140 ms 38.3 k 40 ms 14.7 k 150 ms 42.2 k 50 ms 16.2 k 160 ms 46.4 k 60 ms 17.8 k 170 ms 51.1 k 70 ms 19.6 k 180 ms 56.2 k 80 ms 21.5 k 190 ms 61.9 k 90 ms 23.7 k 200 ms 68.1 k 100 ms 26.1 k t he soft start delay and ramp times can also be set to custom values via the i 2 c /smbus interface. when the ss delay time is set to 0 ms , the device will begin its ramp - up after the internal circuitr y has initialized (approx. 6 ms). when the s oft - start ramp period is set to 0 ms, the output will ramp up as quickly as the output load capacitance will allow. 5.8 switching frequency and pll the zl2105 incorporates an internal phase - locked loop (pll) to clo ck the internal circuitry. the pll can be dri ven by an external clock so urce connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the cfg pin is used to select the operating mode of t he sync pin , configure s eque ncing, and enable tracking. table 12 describes the op erating modes for the sync pin. section 6.12 output sequencing , on page 30 des cribes sequencing and track ing. figure 15 illus trates the typical connections for each sync configuration . table 12 . sync pin function selection cfg pin sync pin function low sync is configured as an input open auto detect mode high sync is configured as an output f sw = 400 khz configuration a: sync output when the s ync pin is configured as an output (cfg pin is tied high), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400 khz) onto the sync pin so other devi ces can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. configuration b : sync input when the sync pin is configured as an input (cfg pin is tied low), the device will automatically check for a clock signal on the sync pin each time the en pin is asserted. the zl2105s oscillator will then synchronize both frequency and phase with the rising edge of the external clock signal. the incoming clock signal must be in the range of 200 khz to 2 mhz with a minimum duty cycle, and must be stable when the en pin is a sserted. see table 3 for a com plete list of performance requirements for the incoming clock signal. z l 2 1 0 5 s s r s s d l y r d l y
zl2105 18 fn6851.2 march 30 , 2011 configuration c: sync auto detect w hen the sync pin is configured in auto detect mode (cfg pin is left open), the device will automatically check for a c lock signal on the sync pin after enable is asserted . - if a valid clock signal is present, the zl2105s oscillator will then synchronize both frequency and phase with the rising edge of the external clock signal. the incoming clock signal must be in the r ange of 200 khz to 2 mhz with a minimum duty cycle, and must be stabl e when the en pin is asserted. see table 3 for a complete list of performance requirements for the incoming clock signal. - if no incoming clock signal is present, the zl2105 will configure the switching frequency according to the state of th e sync pin as listed in table 13 . in this configuration, the sync pin is sampled only on start - up and will not modify its switching frequency if the sync pin is re - configured after start - up (unless the power is recycled). table 13 . switching frequency selection sync pin frequency low 200 khz open 400 khz high 1 mhz resistor see table 14 if the user wishes to run the zl2105 at a frequency not listed in table 13 , the switching frequency can be set using an external resistor, r sync , connected between sync an d s gnd using table 14 . figure 15 . sync pin configurations. z l 2 1 0 5 l o g i c h i g h c f g s y n c 2 0 0 k h z C 2 m h z z l 2 1 0 5 c f g s y n c 2 0 0 k h z C 2 m h z z l 2 1 0 5 n / c c f g s y n c 2 0 0 k h z C 2 m h z a ) s y n c = o u t p u t b ) s y n c = i n p u t z l 2 1 0 5 n / c c f g s y n c z l 2 1 0 5 r s y n c n / c c f g s y n c l o g i c h i g h l o g i c l o w o p e n c ) s y n c = a u t o d e t e c t o r o r
zl2105 19 fn6851.2 march 30 , 2011 table 14 . r sync resistor values f sw r sync f sw r syn 200 khz 10 k 571 khz 28.7 k 222 khz 11 k 615 khz 31.6 k 242 khz 12.1 k 667 khz 34.8 k 267 khz 13.3 k 727 khz 38.3 k 296 khz 14.7 k 889 khz 46.4 k 320 khz 16.2 k 1000 khz 51.1 k 364 khz 17.8 k 1143 khz 56.2 k 400 khz 19.6 k 1333 khz 68.1 k 421 khz 21.5 k 1600 khz 82.5 k 471 khz 23.7 k 2000 khz 100 k 533 khz 26.1 k the swi tching frequency can also be set to any value between 200 khz and 2 mhz using the i 2 c /smbus interface. the available frequencies are bounded by f sw = 8 mhz/n, where 4 n 40 . see application note an 20 13 for details . if multiple zilker labs devices are used together, connecting the sync pins together will force all devices t o synchronize with each other. the cfg pin of one device must set its sync pin as an output and the remaining devices must have their sync pins set as an input. note: the switching frequen cy read back using the appropriate pmbus command will differ slightly from the selected value in table 14 . the difference is due to hardware quantization. 5.9 component selection the zl2105 is a synchronous buck conve rter with integrated mosfets that uses an external inductor and capacitors to perfor m the power conversion process. the proper selection of the external components is critical for optimized performance. for more detailed guidelines regarding component sele ction, refer to application note an 20 11. to select the appropriate external components for the desired performance goals, the power supply requirements listed in table 15 must be known. table 15 . power supply requirements parameter range example value input voltage (v in ) 4.5 C 14.0 v 12 v output voltage (v out ) 0.6 C 5. 5 v 1.2 v output current (i out ) 0 to 3 a 2 a output voltage ripple (v orip ) < 3% of v out 1% of v out output load step (i ostep ) < io 50% of i o output load step rate 10 a/s output deviation due to load step 50 mv maximum pcb temp. 120c 85c desired efficiency 85% other considerations optimize for small size 5.9.1 design goal trade - offs the design of the buck power stage r equires several compromises among size, efficiency, and cost. the inductor core loss increases with frequency, so there is a trade - off between a small output filter made possible by a higher switching frequency and getting b etter power supply efficiency. s ize can be decreased by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through - hole inductors and capacitors; however these components are physically large. to start the design, select a frequency based on table 16 . this frequency is a starting point and may be adjusted as the design progresses. table 16 . circuit design considerations frequency range efficiency circuit size 200 C 400 khz highes t larger 400 C 800 khz moderate smaller 800 khz C 2 mhz lower smallest 5.9.2 inductor selection the output inductor selection process must include several trade - offs. a high inductance value will result in a low ripple current (i opp ), which will reduce output c apacitance and produce a low output ripple voltage, but may also compromise outp ut transient load performance. therefore, a balance must be struck between output ripple and opti mal load transient
zl2105 20 fn6851.2 march 30 , 2011 performance. a good starting point is to select the output i nductor ripple equal to the expected load transient step magnitude (i ostep ): now the output inductance can be calculated using the following equation, where v inm is the maximum input voltage: the average indu ctor current is equal to the maximum output current. the peak inductor current (i l pk ) is calculated using the following equation where i out is the maximum output current: select an inductor rated for the average dc current with a pe ak current rating above t he peak current computed above. in over - current or short - circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some induct ance to protect the load and the internal mosfets from damaging currents in this situation. once an inductor is selected, the dc r and core losses in the inductor are calculated. use the dc r specified in the inductor manufacturers datasheet: i lr ms is given by where i out is the maximum output current. next, calculate the core loss of the selected inductor. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datash eet. add the core loss and the esr loss and compare the total loss to the maximum power dissipation recommendation in the inductor datasheet. 5.9.3 output capacitor selection several trade - offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi - stable (x5r and x7r) dielectric ceramic capacitors, also have rel atively low capac itance values. many designs can use a combination of high capacitance devices and low esr devices. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relative ly large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. as a starting point, apportion one - half of the output ripple voltage to the capacito r esr and the other half to capacitance, as shown in the following equations: use these values to make an initial capacitor selection, using a single or capacitor several capacitors in parallel. 2 lrms ldcr i dcr p 12 2 2 opp out lrms i i i 2 8 orip sw opp out v f i c opp orip i v esr 2 2 opp out lpk i i i opp inm out out out i fsw v v v l 1 ostep opp i i
zl2105 21 fn6851.2 march 30 , 2011 after a ca pacitor has been selected, the resulting output voltage ripple can be calculated using the following equation: because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the v o rip should be less than the desired maximum output ripple. for more information on the performance of the power supply in response to a transient load, refer to application note an 20 11. 5.9.4 input capacitor it is highly recommended that dedicated input capacito rs be used in any point - of - load design, even when the supply is powered from a heavily filtered 5 or 12 v bulk supply from an off - line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from the following equation: without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the i nput capacitors should be rated at 1.4x the ripple current calculated above to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the ma ximum expected input voltage are recommended. 5.9.5 bootstrap capacitor selection the high - side driver boost circuit utilizes an internal schottky diode (d b ) and an external bootstrap capacitor (c b ) to supply sufficient gate drive for the high - side mosfet driver . c b should be a 47 n f ceramic type rated for at least 6.3v. 5.9.6 c v25 selection this capacitor is used to both stabilize and provide noise filtering for the 2.5 v internal power supply. it should be between 4.7 and 10 f, and should use a semi - stable x5r or x7 r dielectric ceramic with a low (less than 10 m ) esr, and should have a rating of 4 v or more. 5.9.7 c vr selection this capacitor is used to both stabilize and provide noise filtering for the 5 v reference supply (v r ). it should be between 4.7 and 10 f, and be a semi - stable x5r or x7r dielectric ceramic capacitor with a low esr less than 10 m , and be rated 6.3 v or more. because the current for the bootstrap supply is drawn from this capacitor, c vr should be sized at least 10x the value of c b so that a dischar ged c b does not cause the voltage on it to dro o p excessively during a c b recharge pulse. 5.9.8 c vr a selection this capacitor is used to both stabilize and provide noise filtering for the analog 5 v reference supply (v r a ). it should be between 2.2 and 10 f, be a semi - stable x5r or x7r dielectric ceramic capacitor with a low esr less than 10 m , and be rated 6.3 v or more. 5.9.9 r vr selection a 91? resistor should be placed between vr and vra to reduce noise and help the stability of the vr and vra regulators over all operating conditions. 5.9.10 thermal considerations in typical applications, the zl2105s high efficiency will limit the internal power d issipation inside the package. however, in applications that require a high ambient operating temperature the user must perform some thermal analysis to ensure that the zl2105s maximum junction temperature is not violated. the zl2105 has a maximum juncti on temperature limit of 12 5c, and the internal over temperature limiting circuitry will force the device to shut down if its junction temp erature exceeds this threshold. in order to calculate the maximum junction temperature, the user must first calculate the power dissipated inside the ic (p q ) as follows: p q = (i load 2 )[r ds(on)qh )(dc)+(r ds(on)ql )(1 - dc )] the maximum operating junction temperature can then be calculated using the following equation: where t pcb is the expected maximum printed circuit board temperature, and jc is the junction - to - case thermal resistance for the zl2105 package. ) 1 ( d d i i out cinrms jc q pcb j p t t max out sw opp opp orip c f i esr i v 8
zl2105 22 fn6851.2 march 30 , 2011 5.10 c urrent sensing and current limit threshold selection it is recommended that the user include a current limiting mechanism in their design to pro tect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload cond ition is imposed on the output. current limiting is accomplished by sensing the curr ent through the circuit during a portion of the duty cycle. the zl2105 incorporates mosfet sensing across the internal low - side mosfet. the user can select one of the three cur rent limit thresholds using the ilim pin according to table 1 7 . table 1 7 . current limit selections ilim pin current limit threshold low 3.0 a open 4.0 a high 4.5 a if the desired current limit threshold is not available in table 1 7 , the current limit threshold can be set in 2 00 ma increments using an external resistor, r lim , connected between the il im pin and sgnd using resistor values from table 18 . the current limit threshold can a lso be set to a custom value via the i 2 c/smbus interface. please refer to application note an 20 13 for further details. table 18 . current limit threshold settings i lim r lim i lim r lim 0.2 a 11 k 2.6 a 34.8 k 0.4 a 1 2 .1 k 2. 8 a 38.3 k 0.6 a 13.3 k 3.0 a 42.2 k 0.8 a 14.7 k 3.2 a 46.4 k 1.0 a 16.2 k 3.4 a 51.1 k 1.2 a 17.8 k 3.6 a 56.2 k 1.4 a 19.6 k 3.8 a 61.9 k 1.6 a 2 1 .5 k 4.0 a 68 . 1 k 1.8 a 23.7 k 4.2 a 75 k 2.0 a 26 .1 k 4.4 a 82.5 k 2.2 a 28.7 k 4.6 a 90.9 k 2.4 a 31.6 k 5.11 loop compensation the zl21 05 operates as a voltage - mode synchronous buck controller wit h a fixed frequency pwm scheme. although the zl2 1 05 uses a digital control loop, it operates much like a traditional analog pwm controller. figure 16 is a simplified block diagram of the zl2 1 05 control loop, which differs from an analog control loop only by the constants in the pwm and compensation b locks. as in the analog controller ca se, the compensation block compares the output voltage to the desired voltage reference and compensation zero e s are added to keep the loop stable. the resulting integrated error signal is used to drive the pwm logic, converting the error signal to a duty c ycle to drive the internal mosfets. figure 16 . control loop block diagram d 1 - d v i n v o u t l c d p w m r c c o m p e n s a t i o n r o z l 2 1 0 5
zl2105 23 fn6851.2 march 30 , 2011 in the zl21 05, the compensation zeros are se t by configuring the fc pin or via the i 2 c/smbus interface once the user has cal culated the required settings. this method eliminates the inaccuracies due to the component tolerances associated with using external resistors and capacitors required with t raditional analog controllers. utilizing the loop compensation sett ings shown in table 19 will yield a conservative crossover frequency at a fixed fraction of the switching frequency (f s /20) and 60 of phase margin. step 1: using the following equation, calculate the resonant frequency of the lc filter, f n . step 2: calculate the esr zero frequency (f zesr ). step 3: based on table 19 , determine the appropriate resistor, r fc . the fc pin can be pin - strapped as low, open, or high. these thr ee positions are the same as the first three entries i n table 19 . the loop compensation coefficients can also be set via the i 2 c/smbus interface. please refer to application note an 20 13 for further details. refer to application note an 20 16 for further technical details on setting loop compensation. 5.12 non - linear response (nlr) settings the zl2 1 05 incorporates a non - linear response (nlr) loop that decreases the response time and the output voltage deviation in the eve nt of a s udden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. this scheme results in a highe r equivalent loop bandwidth than what is possible using a traditional linear loop. when a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the nlr circuitry will force a positive correction signal that will turn on the upper mosfet and quickl y force the output to increase. conversely, a negative load step (i.e. removing a large load current) will cause the nlr circuitry to force a negative correction signal that will turn on the lower mosfet and quickly force the output to decrease. table 19 . resistor settings for loop compensation nlr f n range f zesr range r fc off f sw /60 < f n < f sw /30 f zesr > f sw /10 10 k f sw /10 > f zesr > f sw /30 11 k f sw /30 > f zesr > f sw /60 12.1 k f sw /120 < f n < f sw /60 f zesr > f sw /10 13.3 k f sw /10 > f zesr > f sw /30 14.7 k f sw /30 > f zesr > f sw /60 16.2 k f sw /240 < f n < f sw /120 f zesr > f sw /10 17.8 k f sw /10 > f zesr > f sw /30 19 .6 k f sw /30 > f zesr > f sw /60 21.5 k on f sw /60 < f n < f sw /30 f zesr > f sw /10 23.7 k f sw /10 > f zesr > f sw /30 26.1 k f sw /30 > f zesr > f sw /60 28.7 k f sw /120 < f n < f sw /60 f zesr > f sw /10 31.6 k f sw /10 > f zesr > f sw /30 34.8 k f sw /30 > f ze sr > f sw /60 38.3 k f sw /240 < f n < f sw /120 f zesr > f sw /10 42.2 k f sw /10 > f zesr > f sw /30 46.4 k f sw /30 > f zesr > f sw /60 51.1 k crc f zesr 2 1 c l f n 2 1
zl2105 24 fn6851.2 march 30 , 2011 th e nlr loop is enabled through the fc pin by selecting the appropriate resistor value for the loop compensation settings in table 19 . when operating the zl2105 with a sw itching frequency greater than 1333 khz, nlr must be disabled. 5.13 efficiency optimized drive dead - time control the zl2105 utilizes a closed loop algorithm to optimize the dead - time applied between the gate drive signals for the top and bottom mos fets. in a s ynchronous buck topology, potentially damaging currents can flow in the circuit of both top and bottom mosfets are turned on simultaneously for periods of time exceeding a few nanoseconds, and system efficiency can be adversely affected if both mosfets are turned off for too long. therefore, it is advantageous to minimize the dead - time to provide peak optimal efficiency without compromising system re liability. t he duty cycle of a buck converter is determined to a first - order degree by the input and output v oltage ratio . however, non - idealities exist that cause the real duty cycle to extend beyond the ideal value. dead - time is one of the non - idealities that can be mani pulated to improve efficiency. the zl2105 has an internal algorithm that can continuously ad just the dead - time to optimize duty cycle, thus maximizing efficiency. 6. power management functional description 6.1 input undervoltage lockout the input undervoltage lockout (uvlo) prevents the zl2105 from operating whe n the input falls below a prese t thresho ld, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 4. 5 v and 10.2 v using the uvlo pin. the simplest implementation is to connect the uvlo pin as shown in table 20 . if the uvlo pin is left unconnected, the uvlo threshold will default to 6 .5 v. table 20 . uvlo pin settings pin setting uvlo threshold low 4. 5 v open 6.5 v high 10 . 2 v if the desired uvlo threshold is not on of the list ed choices, the user can configure a threshold between 3.79 v and 13.2 v by connecting a resistor between the uvlo pin and gnd by selecting the appropriate resistor from table 21 . v uvlo can also be set to any value between 3.79 v and 13.2 v via the i 2 c/smbus interface. table 21 . uvlo resistor values uvlo r uvlo uvlo r uvlo 3.79 v 23.7 k 7.42 v 46.4 k 4.18 v 26.1 k 8.18 v 51.1 k 4.59 v 28.7 k 8.99 v 56.2 k 5.06 v 31.6 k 9.90 v 6 1.9 k 5.57 v 34.8 k 10.90 v 68.1 k 6.13 v 38.3 k 12.00 v 75 k 6.75 v 42.2 k 13.20 v 82.5 k once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption 2. cont inue operating for a given delay period, followed by shut down if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdown unt il the fault has been cleared. the user can select a specific number of retry attempts.
zl2105 25 fn6851.2 march 30 , 2011 6.2 power good (pg) and output overvoltage p rotection the zl2105 provides a power good (pg) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. by default, the pg pin w ill assert if the output is within +1 5%/ - 10% of the target voltage. these limits may be changed via the i 2 c/smbus interface. a pg delay period is defined as the time from when all conditions for asserting pg are met and when th e pg pin is actually asserte d. this feature is commonly used instead of an external reset controller to signal the power supply is at its target voltage prior to e nabling any powered circuitry. by default, the zl2105 pg delay is set equal to the soft - start ramp time setting. thus if the soft - start ramp time is set to 10ms, the pg pin will assert 10ms after the output is within its specified tolerance band. the pg delay period can be set independent of the soft - start ramp time via the i 2 c/smbus interface. 6.3 output overvoltage protection the zl2105 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage high er than its prescribed limits. a hardware comparator is used to compare the actual output voltag e (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the vsen voltage exceeds this threshold, the pg pin will de - assert and the device can then respond in a number of ways as follows: 1. initiate a n immediate shutdown un til the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high - side mosfet and turn on the low - side mosfet . the low - side mosfet remains on until the device attempts a restart . the default response from an overvoltage faul t is to immediately shut down. the device will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re - enabled. for continuous overvoltage protection w hen operating from an external clock, the only allowed response is an immediate shutdown. please refer to application note an 20 13 for details on how to select specific overvoltage fault response options via i 2 c/smbus. 6.4 output pre - b ias protection an output p re - bias condition exists when an externally applied voltage is present on a power supplys output before the power supplys control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre - bias condition exists at the output. t he zl2 1 05 provides pre - bias protection by sampling the output voltage prior to initiating an output ramp. if a pre - bias voltage lower than the target voltage exists after the pre - configured delay period has expired , the ta rget voltage is set to match the existing pre - bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the ramp rate set by the ss pin. the actual time the output will take to ramp from the pre - bias volt age to the target voltage will vary depending on the pre - bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre - configured ramp time . se e figure 17 .
zl2105 26 fn6851.2 march 30 , 2011 figure 17 . output responses to pre - bias voltages if a pre - bias voltage higher than the target voltage exists after the pre - configured delay period has expired, the target voltage is set to match the existing p re - bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre - bias voltage. once the pre - configured soft - start ramp period has expired, the pg pin will be asserted (assuming the pre - bias voltage is not highe r than the overvoltage limit). the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre - configured output voltage. if a pre - bias voltage higher than the overvoltage limit exists, the device will not initia te a turn - on sequence and will declare an overvo ltage fault condition to exist. in this case, the device will respond based on the output overvoltage fault response method that has been selected. see section 6.3 output overvoltage protection , for response options due to an overvoltage condition. 6.5 output overc urrent protection the zl2105 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output . once the current limit threshold has been selected (see section 5.10 current limit threshold selection ), the user may determine the desired course of action in re s ponse to the fault condition. the following overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restar t a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an overcurrent fault is an immed iate shutdown of the device. the device will continuously check for the presence of the fault condition, and if the fault condition no longer exists the devi ce will be re - enabled. please refer to application note an 20 13 for details on how to select specific overcurrent fault response options via i 2 c/smbus. 6.6 thermal overload protection the zl2105 includes an on - chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset l imit. the default temperature limit is set to 1 2 5c in the factory, but the user may set the limit t o a different value if desired. the user may select one of the following overtemperature protection response options: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a pre set delay period between attempts. 3. continue operating for a given delay period, followed by shutd own if the fault still exists.
zl2105 27 fn6851.2 march 30 , 2011 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdow n. if the user has configured the device to restart, the device will wait the preset delay period (if so chosen) and will the n check the device temperature. if the temperature has dropped below a threshold that is approx 15c lower than the selected temper ature fault limit, the de vice will attempt to re - start. if the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. the default response from a temperature fault is an im mediate shutdown of the device. the device will continuously check for the fault condition, and once the fault has cleared the zl21 05 will be re - enabled. please refer to application note an 20 13 for details on how to select specific over - temperature fault response options via i 2 c/smbus. 6.7 vol tage tracking numerous high performance systems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply v oltages to power a single die. in most case s, the i/o interface operates at a higher voltage than the c ore and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications . voltage tracking protec ts these sensitive ics by limiting the differential voltage between multiple power supplies during the po wer - up and power down sequence. the zl2105 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required. the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the devices output regulation. figure 18 . tracking modes v o u t v o u t t i m e c o i n c i d e n t r a t i o m e t r i c v t r k v i n v o u t s w z l 2 1 0 5 v t r k v t r k v o u t v o u t t i m e v t r k
zl2105 28 fn6851.2 march 30 , 2011 the zl21 05 offers two mode of tracking as follows: 1. coincident . this mode configures the zl2 1 05 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. 2. ratiometric . this mode configures the zl2 1 05 to ramp its output voltage at a rate that is a percentage of the vo ltag e applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio. figure 18 illus trates the typical connection and the two tracking modes . the master zl2105 device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is no t conf igured for tracking mode. a delay of at least 10 ms must be configured into the master device using the dly pin, and the user may also configure a specif ic ramp rate using the ss pin. tracking mode is enabled through the cfg pin as shown in table 25 on page 30 . any device that is configured for tracking mode will ignore its soft - start delay and ramp time settings (ss and dly pins) and its output will take on the turn - on/turn - off charact eristics of the reference vo ltage present at the vtrk pin. the tracking mode for all other devices can be set by connecting a resistor from the ss pin to ground according to table 22 . all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking mode can also be configured via the i 2 c/smbus interface by using the track_config pmbus command. please refer to application note an 20 13 for more information on configu ring tracking mode using pmbus. 6.8 voltage margining t he zl2105 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn pin is a ttl - compatible input that can be driven directly by a processor i/o pin or other logic - level output. t he zl2105s output will be forced higher than its nominal set point when the mgn pin is driven high, and the output will be force d lower than its nominal set point when the mgn pin is driven low. when the mgn pin is left floating (high impedance), the zl2105s output voltage will be set to its nominal voltage set point determined by the v0 and v1 pins and/or the i 2 c /smbus settings. default m argin limits of v nom 5% are pre - loaded in the factory, but the margin limits can be modified through the i 2 c /smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point det ermined by the v0 and v1 pins. a safety feature prevents the user from configuring t he output voltage to exceed v nom + 10% under any conditions. the margin limits and the mgn pin command can both be set individually through the i 2 c/smbus interface. additionally, the transition rat e between the nominal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an 20 13 for detailed instructions on modifying the margining configurations. table 22 . tracking mode configuration r ss tracking ratio upper track limit ramp - up/ramp - dow n behavior 10 k 100% limited by target voltage output not allowed to decrease before pg 11 k output will always follow vtrk 12.1 k limited by vtrk pin voltage output not allowed to decrease before pg 13.3 k output will always follow vtrk 14.7 k 50% limited by target voltage output not allowed to decrease before pg 16.2 k output will always follow vtrk 17.8 k limited by vtrk pin voltage output not allowed to decrease before pg 19.6 k output will always follow vtrk
zl2105 29 fn6851.2 march 30 , 2011 6.9 i 2 c/smbus communications the zl2105 pro vides an i 2 c/smbus digital interface that enables the user to configure all aspects of the device operation as well as monitor th e input and output parameters. the zl2105 can be used with any standard 2 - wire i 2 c host device. in addition, the device is comp atible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related t o continuous fault monitoring. pull - up resistors are required on the i 2 c/smbus. the zl2105 accepts most standard pmbus commands. 6.10 i 2 c/smbus device addr ess selection when communicating with multiple pmbus devices using the i 2 c/smbus interface, each device must have its own unique address so the host can di stinguish between the devices. the device address can be set according to the pin - strap options liste d in table 23 . address values are right - justified. table 23 . smbus de vice address selection sa pin setting smbus address low 0x20 open 0x21 high reserved if additional device addresses are required, a resistor can be connected to the sa pin according to table 24 to provide up to 25 unique device addresses. table 24 . additional smbus address values smbus address r sa smbu s address r sa 0x2 0 10 k 0x2 d 34.8 k 0x2 1 11 k 0x2 e 38.3 k 0x2 2 12.1 k 0x2 f 42.2 k 0x2 3 13.3 k 0x3 0 46.4 k 0x2 4 14.7 k 0x 3 1 51.1 k 0x2 5 16.2 k 0x 3 2 56.2 k 0x2 6 17.8 k 0x 3 3 61.9 k 0x2 7 19.6 k 0x 3 4 68.1 k 0x2 8 21.5 k 0x 3 5 75 k 0x2 9 23.7 k 0x 3 6 82.5 k 0x2 a 26.1 k 0x 3 7 90.9 k 0x2 b 28.7 k 0x 3 8 100 k 0x2 c 31.6 k 6.11 phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device su ch that not all devices s tart to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requi rements and efficiency losses. since the peak current drawn from the inp ut supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronize d to the same switch ing clock. the cfg pin is used to set the configuration of the sync pin for each device as described in section 5.8 switching frequency and pll , on page 17 .
zl2105 30 fn6851.2 march 30 , 2011 selecting the phase offset for the device is accomplished by selecting a device address according to the following equation: phase offset = device address x 45 for example: a device address of 0x00 or 0x20 would co nfigure no phase offset a device address of 0x01 or 0x21 would configure 45 of phase offset a device address of 0x02 or 0x22 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 337.5 in 22.5 in crements via the i 2 c /smbus interface. r efer to application note an 20 13 for further details. 6.12 output sequencing a group of zilker labs devices (both zl2005 and zl2105) may be configured to power up in a predetermined sequence . this feature is especially use ful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch - up from occurring. multi - device sequencing can be achieved by conf iguring each device through the i 2 c/smbus interface or by using zilker labs patent ed autonomous sequencing mode. autonomous sequencing mode configures sequencing by using events transmitted between devices over the i 2 c/smbus pins scl and sda. no i 2 c or smb us host device is involved in this method , but the scl and sda pins must be interconnected between all devices that the user wishes to sequence using this method. (note: pull - up resistors on scl and sda are required and should be selected using the criteri a in the smbus 2.0 specification ) . the sequencing order is determined using each devices i 2 c/smbus device address. using autonomous sequencing mode (configured using the cfg pin), the devices must exhibit sequential device addresses with no missing addres ses in the chain. this mode will also constrain each device to have a phase offset according to its device address as described in phase spreading. the group will turn on in order starting with the device with the lowest address and will continue through t o turn on each device in the address chain until all devices connected have been turned on. when turning off, the device with the highest address will turn off first followed in reverse order by the other devices in the group. table 25 . cfg pin configurations for sequencing and tracking r cfg sync pin config sequencing configuration 10 k input sequencing and tracking are disabled 11 k auto detect 12.1 k output 14.7 k input device is the first device in a nested sequencing g roup. turn - on order is based on device address. 16.2 k auto detect 17.8 k output 21.5 k input device is a last device in a nested sequencing group. turn - on order is based on device address. 23.7 k auto detect 26.1 k output 31.6 k input de vice is the middle device in a nested sequencing group. turn - on order is based on device address. 34.8 k auto detect 38.3 k output 42.2 k input sequencing is disabled. voltage tracking enabled as defined in table 22 . 46.4 k auto detect 51.1 k output sequencing is configured by connecting a resistor from the cfg pin to ground as described in table 25 . the cfg pin is used to set the configuration of the sync pin as well as to determine the sequencing method and order. refer to section 5.8 switching frequency and pll , on page 17 for more detail s on the operating parameters of the sync pin. multiple device sequencing may also be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. this method plac es fewer restrictions on device address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its device address. note: event based sequencing and fault spreading are broadc ast in address groups o f up to eight zilker labs digital - dc devices. a n address group consists of all devices whose addresses differ in only the three least
zl2105 31 fn6851.2 march 30 , 2011 significant bits of the address. for example, addresses 0x 20, 0x 25 and 0x 27 are all within the same group. addresses 0x 1f, 0x 20 and 0x 28 are all in different groups. device in the same address group can broadcast power on and power down sequencing and fault spreading events with e ach other. devices in different group cannot. the enable pins of all devices in a sequencing grou p must be t ied together and driven high to initiate a sequenced turn - on of the group. enable must be driven low to initiate a sequenced turnoff of the group. r efer to application note an 20 13 for details on sequencing via the i 2 c/smbus interface. 6.13 monitorin g via i 2 c/smbus a system controller can monitor a wide variety of different zl2105 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be asserted when any number of pre - con f igured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: input voltage output voltage output current internal junction temperature temperature o f an external device switching frequency duty cycle please refer to application note an 20 13 for details on how to monitor specific parameters via the i 2 c/smbus interface. 6.14 temperature monitoring using the xtemp pin the zl2105 supports measurement of an ex ternal device temperature using either a thermal diode integrated in a processor, fpga or asic, or using a discrete diode - connected npn transistor such as a 2n3904 or equivalent. figure 19 illustrates the typical c onnections required. figure 19 . external temperature monitoring z l 2 1 0 5 s g n d x t e m p d i s c r e t e n p n 2 n 3 9 0 4 z l 2 1 0 5 s g n d x t e m p e m b e d d e d t h e r m a l d i o d e p f p g a d s p a s i c 1 0 0 p f 1 0 0 p f
zl2105 32 fn6851.2 march 30 , 2011 6.15 non - volatile memory and device security features the zl2105 has internal non - volatile memory where user configurations are stored. integrated security measures e nsure that the user can only restore the device to a level that has been made available to them. refer to section 5.6 start - up procedure , for details on how the device loads stored values from i nternal memory during start - up. during the initialization process, the zl2105 checks for stored values contain ed in its internal memory. the zl2105 offers two internal memory storage units that are accessible by the user as follows: 1. default store : a power supply module m anufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physi cal construction of the module. in this case, the module manufacturer would use the default store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store : the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply s ettings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. please refer to application note an 20 13 for details on how to set specific security measures via the i 2 c/smbus interface.
zl2105 33 fn6851.2 march 30 , 2011 7. package dimensions
zl2105 34 fn6851.2 march 30 , 2011 8. ordering information part number (notes 2 , 3 ) part marking temp range (c) package (pb - free) pkg. dwg. # zl2105alnf 2105 - 40 to +85 36 ld qfn l36.6x6 c zl2105alnft (note 1 ) 2105 - 40 to +85 36 ld qfn l36.6x6 c ZL2105ALNFT1 (note 1 ) 2105 - 40 to +85 36 ld qfn l36.6x6 c zl2105evk2 evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb - free plastic packaged products employ special pb - free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb - free soldering operations). intersil pb - free products are msl classified at pb - free peak reflow temperatures that meet or exceed the pb - free requirements of ipc/jedec j std - 020 3. for moisture sensitivity level (msl), please see device information page for zl2105 . for more information on msl please see t echbrief tb363 . 9. related documentation the following application support documents and tools are available to help simplify your design. item description zl2105evk 2 ev aluation k it C dc? products dc? control loop compensation
zl2105 35 fn6851.2 march 30 , 2011 10. revision history rev. # description date 0.8 preliminary release july 2006 1.0 updated table 1 and table 3 to remove tbds . release to production. 4/12/07 1.1 added r fc to fig. 3. added charge pump cap value to fi gs. 10 and 11 . added r vr to figs. 8 , 9, 10, and 12 . added soa curve on page 9 . added r vr description on page 20. 5/15 /07 1.2 changed max switch ing frequency from 2mhz to 1.2mh z removed r fc from fig. 3. updated soa curve on page 9 . added ferrite bead to ap plications circuit on page 8 added 100pf cap to temp circuit on page 30 11 / 29 /07 1.3 changed max switching frequency from 1.2mhz to 2mhz updated soa curves on page 9 . 1/10/08 1.4 updated ordering information on page 34 corrected ov response description on page 25 may 2008 fn6851.0 assigned file number fn6851 to datasheet as this will be the first release with an intersil file number. replaced header and footer with intersil header and footer. updated disclaimer informa tion to read intersil and its subsidiaries including zilker labs, inc. no changes to datasheet content february 2009 fn6851.1 added following statement to disclaimer on page 36 : this product is subject to a license from power one, inc. related to digi tal power technology as set forth in u.s. patent no. 7,000,125 and other related patents owned by power one, inc. these license rights do not extend to stand - alone pol regulators unless a royalty is paid to power one, inc. december 2010 fn6851.2 page 3, table 1, 3rd entry, high side supply voltage, change d max value from 30 to 25. page 4, table 3, idss shutdown current, change d max limit from 1 to 2. page 4, table 3, remove d row "logic input bias current" and replace d with "logic input current" conditions "en, scl, sda pins" min - 250 max 250 unit na page 4, table 3, remove d row "mgn pin current" pages 4 - 5 , table 3, add ed footnote "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." page 34, up dated ordering information. added zl2105alnf , ZL2105ALNFT1, zl2105evk2, tape and reel note, pb - free note based on lead finish and msl note. changed pkg. dwg. # from l36.6x6a to l36.6x6c page 34, corrected application note numbers in related documentation . page 33, updated package outline drawing from l36.6x6a to l36.6x6c (max dimension in side view changed from 0.90 to 1.00) march 2011
zl2105 36 fn6851.2 march 30 , 2011 zilker labs, inc. 900 s. capital of texas highway suite 250 austin, tx 78746 tel: 512 - 382 - 8300 fax: 512 - 382 - 8329 www.intersil.com/zilkerla bs/ ? 2008, zilker labs, inc. all rights reserved. zilker labs, digital - dc, and the zilker labs logo are trademarks of zilker labs, inc. all other products or brand names mentioned herein are trademarks of their respective hold - ers. this document contains information on a product under development. specifications are subject to change with - out notice. pricing, specifications and availability are subject to change without notice. please see www.zilker - labs.com for updated information. this product is not intended for u se in connection with any high - risk activity, including without limitation, air travel, life critical medical operations, nuclear facilities or equipment, or the like. the reference designs contained in this document are for reference and example purposes only. the refer - ence designs are provided "as is" and "with all faults" and intersil corporation and its subsidiaries including zilker labs, inc. disclaims all warranties, whether express or implied. zilker labs shall not be liable for any damages, whethe r direct, indirect, consequential (including loss of profits), or otherwise, resulting from the reference designs or any use thereof. any use of such reference designs is at your own risk and you agree to indemnify intersil corporation and its subsidiarie s including zilker labs, inc. for any damages resulting from such use. this product is subject to a license from power one, inc. related to digital power technology as set forth in u.s. patent no. 7,000,125 and other related patents owned by power one, inc . these license rights do not extend to stand - alone pol regulators unless a royalty is paid to power one, inc.

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